1. Field of the Invention
This invention relates to differential amplifiers. More particularly, this invention relates to differential amplifiers with circuitry to increase output voltage gain.
2. Description of the Related Art
FIG. 1 shows a conventional differential amplifier. The differential amplifier includes PNP transistors 100 and 102 with input voltages V.sub.IN and V.sub.INB received at their respective bases, outputs V.sub.OUT and V.sub.OUTB provided at their respective collectors, and emitters connected to a current source 104.
Transistors 100 and 102 are shown as PNP transistors to emphasize the undesirability of Early Voltage, because PNP transistors typically have a much lower Early Voltage than NPN transistors and provide a more dominant limitation on output voltage gain. Transistors 100 and 102 may, however, be NPN transistors, and the Early Voltage will still limit output voltage gain.
With sizes of transistors 100 and 102 being equal and loading at the outputs V.sub.OUT and V.sub.OUTB being equal, voltage gain of a differential amplifier can be expressed as V.sub.GAIN =g.sub.m R.sub.Leff, where g.sub.m is the transconductance of one the bipolar transistors 100 or 102, and R.sub.Leff is the effective load impedance at one of the outputs of the transistor, such as at V.sub.OUT or V.sub.OUTB. In general, R.sub.Leff is the parallel combination of the actual load, such as provided by resistors 106 or 108, and the output impedance of one of the transistors of the differential amplifier, such as 100 or 102. The highest gain can be achieved when the actual load impedance is infinite, or at least substantially higher than a transistor output impedance.
FIG. 2 illustrates that to provide an actual load with a very high impedance, ideal current sinks 206 and 208 may be used in place of load resistors 106 and 108 of FIG. 1. With the actual load impedance of infinity using ideal current sinks 206 and 208, the highest obtainable voltage gain is then limited solely by the output impedance of transistors 100 and 102. Gain for the circuit of FIG. 2 can, thus, be simplified to V.sub.gain =V.sub.EARLY /Vt, where Vt is KT/q=T/11,600, with T being temperature in Kelvin and V.sub.EARLY being the forward Early Voltage of one of the transistors of the differential amplifier such as transistor 100 or transistor 102. Note that components carried over from FIG. 1 to FIG. 2 are similarly labeled, as will be components carried over in subsequent drawings.
FIG. 3 illustrates circuitry conventionally used for providing current sinks 206 and 208 of FIG. 2, but with a finite yet very high effective output impedance. As shown, current sink 206 is provided by an NPN transistor 306 having a collector connected to the collector of transistor 102, and an emitter connected through a resistor 316 to a lower power supply rail (V-). Current sink 208 is provided by an NPN transistor 308 having a collector connected to the collector of transistor 100, and an emitter connected through a resistor 318 to V-. Bases of transistors 306 and 308 are provided by a voltage reference V.sub.REF. Use of degeneration, or negative feedback provided by resistors 316 and 318 on the emitters of the NPN current sink transistors 306 and 308 ensures an NPN output impedance vastly greater than the output impedance of one of PNP transistors 101 or 102.
For maximizing gain, the Early Voltage of the PNP transistors needs to be as high as possible. To achieve a higher frequency response, in general, transistor base widths are made thinner. One undesirable effect of having a thinner transistor base width is that the forward Early Voltage becomes lower.